91漫画

Zustandsautomaten k枚nnen sehr elegant in VHDL beschrieben werden.

Hier ein Automat, der die Sequenz 鈥�101鈥� erkennt und dann am Ausgang eine 鈥�1鈥� ausgibt. Ein Moore Automat entsteht, wenn die Ausgangssignale nur vom State und nicht vom Eingangssignal abh盲ngen.

library ieee;
use ieee.std_logic_1164.all;
 
entity automat is 
  port (
    clk_i:            in std_ulogic;
    reset_ni:         in std_ulogic;
    in_i:             in std_ulogic;  
    out_o:            out std_ulogic 
  );
end; 
 
architecture rtl of automat is  
  type state_type is (start_s, erste_eins_s, null_in_der_mitte_s, fertig_s);
  signal current_state, next_state : state_type;
begin
 
  next_state_and_output_p : process(current_state, in_i)
  begin
    out_o <= '0';
    next_state <= current_state; 
    case current_state is
      when start_s =>
        if in_i = '1' then
          next_state <= erste_eins_s;
        end if;
      when erste_eins_s  =>
        if in_i = '0' then
          next_state <= null_in_der_mitte_s;
        else
          next_state <= erste_eins_s; 
        end if; 
      when null_in_der_mitte_s  =>
        if in_i = '1' then
          next_state <= fertig_s; 
        else
          next_state <= start_s;
        end if;
      when fertig_s => 
        out_o <= '1';
        if in_i = '1' then 
          next_state <= erste_eins_s;
        else
          next_state <= start_s;
        end if; 
    end case; 
  end process next_state_and_output_p;  
 
  -- The sequential process for flipflop instantiation
  -- All signal assignments in this process will result in flipflops.
  state_reg_p : process (clk_i, reset_ni)
  begin
    if reset_ni = '0' then
      current_state <= start_s;
    elsif rising_edge(clk_i) then
      current_state <= next_state; 
    end if; 
  end process state_reg_p;    
 
end architecture;

Und hier ist eine geeignete Testbench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
 
entity automat_tb is 
  port (
    clk_i:            in std_ulogic;
    reset_ni:         in std_ulogic;
    in_i:             in std_ulogic;  
    out_o:            out std_ulogic 
  );
end; 
 
architecture beh of automat_tb is
 
component automat is 
  port (
    clk_i:            in std_ulogic;
    reset_ni:         in std_ulogic;
    in_i:             in std_ulogic;  
    out_o:            out std_ulogic 
  );
end component;
 
signal clk, reset, stim, output : std_ulogic; 
 
begin
 
-- This process generates the clock
clk_p : process
begin
  clk <= '0';
  wait for 5 ns;
  clk <= '1';
  wait for 5 ns;
end process;
 
-- Here the automat is instantiated as the device under test
dut: automat 
port map (
  clk_i           => clk,
  reset_ni        => reset,
  in_i            => stim,
  out_o           => output
);
 
 
test : process
begin
  reset <= '0';
  -- Wait for some time
  wait for 100 ns; 
 
  wait until falling_edge(clk);
  -- Reset Release
  reset <= '1'; 
  -- Now the positive 101 Sequence
  stim <= '1';
  wait until falling_edge(clk);
 
  stim <= '0';
  wait until falling_edge(clk);
 
  stim <= '1';
  wait until falling_edge(clk);
 
  stim <= '0';
  wait until falling_edge(clk);
  wait until falling_edge(clk);
 
  wait; 
end process test; 
 
 
end architecture;