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dt-code-vecnum [2011/01/13 08:34] beckmanf created |
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| === VHDL Code für Arrays und Arithmetik === | === VHDL Code für Arrays und Arithmetik === | ||
| + | == Arrays == | ||
| + | Im folgenden ein Beispiel für Arrays - hier mit einem Schieberegister, das | ||
| + | nach links und rechts schieben, sowie um 2 Stellen nach links rotieren kann. | ||
| <code vhdl> | <code vhdl> | ||
| Line 12: | Line 15: | ||
| reset_ni: in std_ulogic; | reset_ni: in std_ulogic; | ||
| load_i: in std_ulogic; | load_i: in std_ulogic; | ||
| - | shift_right_i: in std_ulogic;Ìý | + | shift_right_i: in std_ulogic; -- "11111000" -> "01111100"Ìý |
| - | shift_left_i: in std_ulogic; | + | shift_left_i: in std_ulogic; -- "11111000" -> "11110000" |
| rotate_left_by2_i: in std_ulogic; -- "11111000" -> "11100011" | rotate_left_by2_i: in std_ulogic; -- "11111000" -> "11100011" | ||
| data_i: in std_ulogic_vector(7 downto 0); | data_i: in std_ulogic_vector(7 downto 0); | ||
| Line 33: | Line 36: | ||
| end process seq_p; | end process seq_p; | ||
| - | comb_p : process(load_i, sr) | + | comb_p : process(load_i, sr, data_i, shift_left_i, shift_right_i, rotate_left_by2_i) |
| begin | begin | ||
| new_sr <= sr; | new_sr <= sr; | ||
| if load_i = '1' then | if load_i = '1' then | ||
| - | sr <= data_i | + | new_sr <= data_i; |
| elsif shift_right_i = '1' then | elsif shift_right_i = '1' then | ||
| new_sr(7) <= '0'; | new_sr(7) <= '0'; | ||
| Line 51: | Line 54: | ||
| </code> | </code> | ||
| + | |||
| + | == Signed und Unsigned == | ||
| + | Mit dem IEEE numeric.std package können Vektoren auch als Zahlen interpretiert werden. | ||
| + | Dies entspricht | ||
| + | |||
| + | |||
| + | |||
| + | <code vhdl> | ||
| + | use ieee.std_logic_1164.all; | ||
| + | use ieee.numeric_std.all; | ||
| + | |||
| + | architecture rtl of compute is | ||
| + | signal a, b : std_ulogic_vector(15 downto 0); | ||
| + | signal u, v, w : signed(15 downto 0); | ||
| + | signal x, y, z : unsigned(15 downto 0); | ||
| + | begin | ||
| + | |||
| + | -- Umwandlung in verschiedene Typen durch Casts | ||
| + | -- Bei diesen Casts entstehen keine Schaltungen. Die Vektoren werden nur anders interpretiert. | ||
| + | u <= signed(a); | ||
| + | x <= unsigned(b); | ||
| + | b <= std_ulogic_vector(y); | ||
| + | |||
| + | -- Signed und Unsigned Typen werden Vektoren zugewiesen | ||
| + | u <= "1111000011110000"; | ||
| + | x <= "1010101000001111"; | ||
| + | |||
| + | -- Mit Signed und Unsigned Typen kann man rechnen | ||
| + | z <= x + y; | ||
| + | z <= x - y; | ||
| + | z <= x * y; | ||
| + | z <= x + 13; | ||
| + | u <= 17 + v; | ||
| + | |||
| + | -- Und man kann die Arrays vergleichen. Entweder Array mit Array oder Array mit Integer | ||
| + | |||
| + | z <= x when u > v else y; | ||
| + | z <= x when u = v else y; | ||
| + | z <= x when u <= 5 else y; | ||
| + | |||
| + | end architecutre; | ||
| + | </code> | ||
| + | |||
| + | == Integer Zahlen == | ||
| + | |||
| + | Es gibt in VHDL auch den Typen integer, der Zahlen darstellt. Mit integer können auch gerechnet und verglichen werden. | ||
| + | Integer Zahlen können auch in die Typen signed und unsigned umgewandelt werden | ||
| + | |||
| + | <code vhdl> | ||
| + | library ieee; | ||
| + | use ieee.std_logic_1164.all; | ||
| + | use ieee.numeric_std.all; | ||
| + | |||
| + | architecture rtl of compute is | ||
| + | signal a, b, c : integer range 0 to 230; | ||
| + | signal u, v, w : signed(7 downto 0); | ||
| + | signal x, y, z : unsigned(7 downto 0); | ||
| + | begin | ||
| + | |||
| + | a <= 5; | ||
| + | b <= a + 3 when c >= 5 else 9; | ||
| + | |||
| + | -- Umwandlung von Integer nach Signed und Unsigned | ||
| + | -- Bei der Umwandlung muss man angeben wieviele Elemente der Ausgangsvektor haben soll | ||
| + | x <= to_unsigned(a,8); -- 8 ist die Breite des Arrays x. | ||
| + | u <= to_signed(a,8); | ||
| + | |||
| + | -- Umwandlung von signed, unsigned in integer | ||
| + | a <= to_integer(u); | ||
| + | b <= to_integer(x); | ||
| + | |||
| + | end architecture; | ||
| + | </code> | ||
| + | |||