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dt-code-sequ [2012/01/18 11:08] beckmanf typos |
dt-code-sequ [2014/01/08 11:02] (current) beckmanf flipflop process -> concurrent |
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| Line 16: | Line 16: | ||
| in_i : in std_ulogic; | in_i : in std_ulogic; | ||
| out_o : out std_ulogic); | out_o : out std_ulogic); | ||
| - | end; | + | end entity flipflop; |
| architecture rtl of fliplfop is | architecture rtl of fliplfop is | ||
| Line 33: | Line 33: | ||
| out_o <= q; | out_o <= q; | ||
| - | end; | + | end architecture rtl; Ìý |
| + | &±ô³Ù;/³¦´Ç»å±ð&²µ³Ù;Ìý | ||
| + | Ìý | ||
| + | Ein Flipflop kann alternativ mit einem concurrent statement beschrieben werden. Ìý | ||
| + | Ìý | ||
| + | <code vhdl>Ìý | ||
| + | entity flipflop is Ìý | ||
| + | port(Ìý | ||
| + | clk : in std_ulogic;Ìý | ||
| + | reset_n : in std_ulogic;Ìý | ||
| + | in_i : in std_ulogic; Ìý | ||
| + | out_o : out std_ulogic);Ìý | ||
| + | end entity flipflop;Ìý | ||
| + | Ìý | ||
| + | architecture rtl of fliplfop isÌý | ||
| + | signal q : std_ulogic;Ìý | ||
| + | beginÌý | ||
| + | Ìý | ||
| + | q <= '0' when reset_n = '0' else in_i when rising_edge(clk); Ìý | ||
| + | Ìý | ||
| + | out_o <= q; | ||
| + | end architecture rtl; | ||
| </code> | </code> | ||
| | | ||
| Line 48: | Line 69: | ||
| begin | begin | ||
| - | ff_p : process(clk, reset_n)Ìý | + | q <= '0' when reset_n = '0' else new_q when rising_edge(clk); |
| - | beginÌý | + | |
| - | if reset_n = '0' thenÌý | + | |
| - | q <= '0';Ìý | + | |
| - | elsif rising_edge(clk) thenÌý | + | |
| - | q <= new_q; Ìý | + | |
| - | end if;Ìý | + | |
| - | end process ff_p; | + | |
| new_q <= not q; | new_q <= not q; | ||
| - | end; | + | end architecture rtl; |
| </code> | </code> | ||
| Line 76: | Line 90: | ||
| entity strangecnt is | entity strangecnt is | ||
| port ( | port ( | ||
| - | clk_i : in std_ulogic;Ìý | + | clk : in std_ulogic;Ìý |
| - | reset_ni : in std_ulogic; | + | rst_n : in std_ulogic; |
| s_i : in std_ulogic; | s_i : in std_ulogic; | ||
| cnt0_o : out std_ulogic; | cnt0_o : out std_ulogic; | ||
| Line 88: | Line 102: | ||
| signal l : std_ulogic; | signal l : std_ulogic; | ||
| begin | begin | ||
| - | seq_p : process(clk_i, reset_ni)Ìý | + | Ìý |
| - | beginÌý | + | c0 <= '0' when rst_n = '0' else c0_new when rising_edge(clk); Ìý |
| - | if reset_ni = '0' thenÌý | + | c1 <= '0' when rst_n = '0' else c1_new when rising_edge(clk); |
| - | c0 <= '0';Ìý | + | |
| - | c1 <= '0'; Ìý | + | |
| - | elsif rising_edge(clk_i) thenÌý | + | |
| - | c0 <= c0_new;Ìý | + | |
| - | c1 <= c1_new; Ìý | + | |
| - | end if;Ìý | + | |
| - | end process seq_p; | + | |
| c0_new <= not c0; | c0_new <= not c0; | ||