library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera;
use altera.altera_primitives_components.all;
entity top is
port (
CLOCK_24: in std_ulogic_vector(1 downto 0);
KEY: in std_ulogic_vector(3 downto 0);
SW: in std_ulogic_vector(9 downto 0);
I2C_SCLK: out std_ulogic;
I2C_SDAT: inout std_logic;
AUD_ADCLRCK: out std_ulogic;
AUD_ADCDAT: in std_ulogic;
AUD_DACLRCK: out std_ulogic;
AUD_DACDAT: out std_ulogic;
AUD_XCK: out std_ulogic;
AUD_BCLK: out std_ulogic;
LEDR: out std_ulogic_vector(9 downto 0);
HEX0: out std_ulogic_vector(6 downto 0)
);
end;
architecture struct of top is
component i2c_sub is
port (
clk_i: in std_ulogic;
reset_ni: in std_ulogic;
i2c_clk_o: out std_ulogic;
i2c_dat_o: out std_ulogic;
i2c_dat_i: in std_ulogic
);
end component;
component adcintf is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
en_i : in std_ulogic;
valid_o : out std_ulogic;
data_o : out std_ulogic_vector(15 downto 0);
start_i : in std_ulogic;
ser_dat_i : in std_ulogic);
end component;
component dacintf is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
load_i : in std_ulogic;
data_i : in std_ulogic_vector(15 downto 0);
en_i : in std_ulogic;
ser_dat_o : out std_ulogic);
end component;
component ringbuf is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
en_i : in std_ulogic;
data_i : in std_ulogic_vector(15 downto 0);
data_o : out std_ulogic_vector(15 downto 0));
end component;
component bclk is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
bclk_o : out std_ulogic;
bclk_falling_edge_en_o : out std_ulogic);
end component;
component fsgen is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
bclk_falling_edge_en_i : in std_ulogic;
fs_o : out std_ulogic);
end component;
component mclk is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
mclk_o : out std_ulogic);
end component;
signal clk, reset_n : std_ulogic;
signal i2c_dat_o : std_ulogic;
signal i2c_dat_i : std_ulogic;
signal framesync : std_ulogic;
signal bclk_falling_edge_en : std_ulogic;
signal adc_valid : std_ulogic;
signal dac_data, adc_data : std_ulogic_vector(15 downto 0);
begin
reset_n <= KEY(0);
clk <= CLOCK_24(0);
i2c_sub_i0 : i2c_sub
port map (
clk_i => clk,
reset_ni => reset_n,
i2c_clk_o => I2C_SCLK,
i2c_dat_o => i2c_dat_o,
i2c_dat_i => i2c_dat_i);
mclk_i0 : mclk
port map(
clk_i => clk,
reset_ni => reset_n,
mclk_o => AUD_XCK);
bclk_i0 : bclk
port map (
clk_i => clk,
reset_ni => reset_n,
bclk_o => AUD_BCLK,
bclk_falling_edge_en_o => bclk_falling_edge_en);
fsgen_i0 : fsgen
port map (
clk_i => clk,
reset_ni => reset_n,
bclk_falling_edge_en_i => bclk_falling_edge_en,
fs_o => framesync);
dacintf_i0 : dacintf
port map (
clk_i => clk,
reset_ni => reset_n,
load_i => framesync,
data_i => dac_data,
en_i => bclk_falling_edge_en,
ser_dat_o => AUD_DACDAT);
adcintf_i0 : adcintf
port map (
clk_i => clk,
reset_ni => reset_n,
valid_o => adc_valid,
data_o => adc_data,
start_i => framesync,
en_i => bclk_falling_edge_en,
ser_dat_i => AUD_ADCDAT);
AUD_DACLRCK <= framesync;
AUD_ADCLRCK <= framesync;
ringbuf_i0 : ringbuf
port map (
clk_i => clk,
reset_ni => reset_n,
en_i => adc_valid,
data_i => adc_data,
data_o => dac_data);
LEDR(9 downto 0) <= std_ulogic_vector(abs(signed(dac_data(15 downto 6))));
HEX0 <= "0000000";
-- i2c has an open-drain ouput
i2c_dat_i <= I2C_SDAT;
i2c_data_buffer_i : OPNDRN
port map (a_in => i2c_dat_o, a_out => I2C_SDAT);
end; -- architecture